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What is NanoScale[Features]DownloadPurchaseSupport

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NanoScale Features - Architecture

Dual Mode

Dual Mode Processors and RTOS are basically used in two disciplines: Digital Signal Processing (DSP) and Control Processing. These two purposes require completely different needs. Control processing focus on complex interactions between many external events and the different tasks of the application. In such software, the RTOS offers an abstraction from the complexity of the underlying processor. An important part of the OS relies on its scheduling capabilities.

In contrast, DSP are used for performance and throughput. In such applications, large amount of data must be processed at very high speeds. Dedicated algorithms sustain these requirements, based on specific hardware features for fast calculus and memory access. In this context, ISR become the most critical part of this kind of application.

Using a traditional RTOS for DSP needs result in a trade-off between flexibility and performances. Indeed, context switching resulting from the activation of the different DSP tasks are expensive operations.

Mixing the two worlds is possible with a Dual-Mode RTOS like NanoScale. Such OS combines a traditional task-based architecture for real-time control processing, with a specialized mean for DSP and data-flow operations. The architecture makes a separation of concern between both of them, but still provides a common API for system calls.


Segmented Architecture

Segmented Architecture Any embedded software needs to manage Interrupt Requests (IRQ) generated by the processor. However, communication between an ISR and a RTOS is not as easy as it seems. Indeed, any OS often needs to perform atomic operations when managing its internal structure. This kind of operation is typically triggered by user application calling an underlying OS service. If an interrupt happens during such atomic operation, and try to access the same critical structure, the results could be catastrophic.

The unified architecture solves this issue by briefly disabling interrupts when the OS need to access critical data. The drawback of this method is the possible delay before an interrupt is serviced. Indeed, disabling interrupts can add some unexpected latency before ISR execution, and can even lead to lost of interrupts.


Unified Architecture

To avoid such latency, NanoScale implements the so-called segmented architecture. NanoScale never disables interrupts, reducing RTOS latency to zero. In addition, NanoScale still allows communications between ISR and the OS. This architecture allows both efficient interrupt management and flexible programming model.


Segmented Architecture

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